Sr Latch Timing Diagram. Slide 12 of 62. Following the convention the prime in s and r denotes that these inputs are active low.
February 6 2012 ece 152a digital design principles 25 the gated sr latch cont. In addition to the two outputs q and q there are two inputs s and r for set and reset respectively. In this video i have solved an example on sr latch timing diagram.
Following the convention the prime in s and r denotes that these inputs are active low.
Following the convention the prime in s and r denotes that these inputs are active low. In addition to the two outputs q and q there are two inputs s and r for set and reset respectively. In this video i have solved an example on sr latch timing diagram. In this video i have solved an example on sr latch timing diagram.
