Sr Latch Nand Timing Diagram. These bi stable combinations of logic gates form the basis of comput. When both inputs are de asserted the sr.
The function of such a circuit is to latch the value created by the input signal to the device and hold. A circuit using nand gates. Construction of sr flip flop by using nand latch this method of constructing sr flip flop uses.
Working of sr nand latch.
The circuit shown below is a basic nand latch. The time sequence at right shows the conditions under which the set and reset inputs cause a state change and when they don t. These bi stable combinations of logic gates form the basis of comput. By using nand latch.
