Sr Flip Flop Circuit Diagram Using Nand Gates. The rs flip flop actually has three inputs set reset and its current output q relating to its current state. In nand gate we will get output as 0 only if both the inputs are high and if any of the input is high or both the input is low we will receive logic 1.
It can be constructed from a pair of cross coupled nor or nand logic gates. But this flip flop affects the outputs only when positive transition of the clock signal is applied instead of active enable. This will set the flip flop and hence q will be 1.
The lower nand gate is disabled and the upper nand gate is enabled if q is at 1 as a result we will be able to set the flip flop q 1 q 0 if not already set.
When using static gates as building blocks the most fundamental latch is the simple sr latch where s and r stand for set and reset. The rs flip flop actually has three inputs set reset and its current output q relating to its current state. The following table shows the state table of sr flip flop. If q 0 the lower nand gate is disabled the upper nand gate is enabled.
