Siso Shift Register Circuit Diagram. Figure 1 shows a n bit synchronous siso shift register sensitive to positive edge of the clock pulse. This block diagram consists of three d flip flops which are cascaded.
The output is also obtained on a single output line in a same serial fashion. The logic circuit diagram below shows a generalized serial in serial out shift register. The logic circuit diagram below shows a generalized serial in serial out shift register.
The output is also obtained on a single output line in a same serial fashion.
All these flip flops are synchronous with each other since the same clock signal is applied to each one. This type of shift register also acts as a temporary storage device or it can act as a time delay device for the data with the amount of time delay being controlled by the number of stages in the register 4 8 16 etc or by varying the application of the clock pulses. A serial in serial out shift register may be one to 64 bits in length longer if registers or packages are cascaded. Logic diagram here x i is serial input of this register x i0 x i1 x i2 x i3 are the parallel inputs of this register y i is serial output of this register and y 0 y 1 y 2 y 3 are the parallel outputs.
