Gated Sr Latch Diagram. The circuit diagram of sr latch is shown in the following figure. Here the inputs are complements of each other.
The design of d latch with enable signal is given below. A synchronous sr latch sometimes clocked sr flip flop can be made by adding a second level of nand gates to the inverted sr latch or a second level of and gates to the direct sr latch. This circuit has two inputs s r and two outputs q t q t.
The truth table for the d latch is.
When the e 0 the outputs of the two and gates are forced to 0 regardless of the states of either s or r. Gated d latch d latch is similar to sr latch with some modifications made. Consequently the circuit behaves as though s and r were both 0 latching the q and not q outputs in their last states. When the e 0 the outputs of the two and gates are forced to 0 regardless of the states of either s or r.
