Flash Adc Block Diagram. Figure 1 shows a typical flash adc block diagram. 3 vin vout vr vout vin vr vin vm vout vin vout vm voltage comparator differential input vr is provided by a voltage reference source external to the voltage comparator.
Figure 1 block diagram of the proposed tiq based flash adc. A resistive divider with 2 n resistors provides the reference voltage. The sample amplitude value is maintained and held in the hold block.
A resistive divider with 2 n resistors provides the reference voltage.
Each comparator compares vin to a different reference voltage starting with vref 1 2 lsb. Inverter fixed by the transistor sizes. The reference voltage for each comparator is one least significant bit lsb greater than the reference voltage for the comparator immediately below it. For an n bit converter the circuit employs 2 n 1 comparators.
