Clocked Sr Flip Flop Circuit Diagram. It is a clocked flip flop. Again this gets divided into positive edge triggered sr flip flop and negative edge triggered sr flip flop.
For this a clocked s r flip flop is designed by adding two and gates to a basic nor gate flip flop. There are however some problems with the operation of this most basic of flip flop circuits. Thus sr flip flop is a controlled bi stable latch where the clock signal is the control signal.
However in row 5 both inputs are 0 which makes both q and q 1 and as they are no longer opposite logic states although this state is possible in practical circuits it is not allowed.
The following table shows the state table of sr flip flop. This means that in clocked circuits the outputs do not change as soon as the inputs change but must wait for a clock signal before the output state can change. It is a clocked flip flop. Thus the output has two stable states based on the inputs which have been discussed.
