Clock Divider Circuit. It takes three clock cycles before the output of the counter equals the pre defined constant 3. Displaystyle f out frac f in n where.
For example a clock divider could drive an output low while counting five 100mhz input clock cycles then drive the signal high while counting another five cycles and so on in an endlessly repeating sequence to create a 10mhz clock. After the first stage the frequency became frac 100mhz 2 50 mhz. F o u t f i n n.
With this circuit we can actually divide the clock by cascading the previous circuit as displayed in fig.
The divider circuit counts input clock cycles and drives the output clock low and then high for some number of input clock cycles. A frequency divider also called a clock divider or scaler or prescaler is a circuit that takes an input signal of a frequency f i n. Let s assume that the pre defined number is 3 and the output of clock divider clk div is initialized to 0. It takes three clock cycles before the output of the counter equals the pre defined constant 3.
