4 Bit Parallel In Serial Out Shift Register Timing Diagram. Sn74ls395a parallel in parallel out 4 bit shift register. The circuit uses d flip flops and nand gates for entering data ie writing to the register.
Now from above 4 bit parallel in serial out shift register we can see a b c and d are the four parallel data input lines and shift load sh ld is a control input that allows the four bits of data at a b c and d inputs to enter into the register in parallel or shift the data in serial when shift load is high and gates g1 g3 and g5 are enabled allowing the data bits to shift. This register can be used to store and shift a 4 bit word with the write shift ws control input controlling the mode of operation of the shift register. Assume that the 4 bit data is 1011.
Directly above is the ansi symbol for the 74ls395.
D0 d1 d2 and d3 are the parallel inputs where d0 is the most significant bit and d3 is the least significant bit. This register can be used to store and shift a 4 bit word with the write shift ws control input controlling the mode of operation of the shift register. Serial in serial out shift registers delay data by one clock time for each stage. Directly above is the ansi symbol for the 74ls395.
